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#	Item
21	White paper Top 10 Ways to Spice up DSD Efficiency and Sell More Are your Profits Perishable? Are your out-of-stocks Add to Reading List Source URL: www.mirnah.com Language: English - Date: 2010-12-15 09:57:57 Surveillance Intermec Radio-frequency identification Personal digital assistant Direct store delivery Barcode Automatic identification and data capture Technology Humanâ€“computer interaction
22	Datasheet FineSim Multi-Core/Multi-Machine Enabled Full-Chip Circuit-Level Simulation Introduction Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:51 Electronic circuit simulation SPICE Field-programmable gate array Multi-core processor Logic simulation Synopsys Simucad Electronic engineering Digital electronics Electronic design automation
23	Datasheet CustomSim High-performance, high-capacity FastSPICE simulation Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-18 14:15:51 Electronic circuit simulation SPICE Synopsys Power network design Logic simulation Verilog Static timing analysis Reliability engineering Silvaco Electronic engineering Digital electronics Electronic design automation
24	White Paper Benefits of Using ESP in Memory Designs May 2010 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-04 07:15:42 Hardware description languages Logic design Logic simulation VHDL Standard cell Functional verification SPICE Verilog Simulation Electronic engineering Electronic design automation Digital electronics
25	Spice Up Your Photography WEB VS. PRINT InfoPathways, Inc. www.infopathways.com 25 Liberty Street Add to Reading List Source URL: www.infopathways.com Language: English - Date: 2012-07-26 09:04:54 Image processing Computer graphics Digital media Computer printing Dots per inch Pixel density Pixel Photo manipulation Digital photography Digital imaging Visual arts
26	Datasheet SiliconSmart Comprehensive Cell, I/O and Memory Characterization Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:32:38 Standard cell Signoff SPICE Verilog Electronic circuit simulation Synopsys Signal integrity Simucad Electronic engineering Electronic design automation Digital electronics
27	Datasheet NanoTime Transistor-level Static Timing Analysis Solution for Custom Designs Overview Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2015-02-27 00:06:11 Signoff Synopsys Static timing analysis Signal integrity Electronic circuit simulation Delay calculation Logic simulation Parasitic extraction SPICE Electronic engineering Electronic design automation Digital electronics
28	Saber Accelerates Robust Design ® Predictable. Repeatable. Reliable. Proven. The Cutting Edge Add to Reading List Source URL: www.synopsys.com Language: English Logic design Operations research Hillsboro Oregon Synopsys Simulation SPICE Logic simulation VHDL-AMS Virtual prototyping Electronic engineering Electronic design automation Digital electronics
29	Technical Backgrounder CustomExplorer Ultra Automated Regression for Mixed-Signal Verification April 2011 Add to Reading List Source URL: www.synopsys.com Language: English - Date: 2014-11-07 14:40:27 Logic design Hardware description languages SystemVerilog Verilog SPICE Netlist Logic simulation Simucad Electronic engineering Electronic design automation Digital electronics
30	Liberate MX Improve your view… Liberate MX extends Altos’ ultra-fast standard cell and I/O library characterization capabilities to cover larger macro blocks such as memory, mixed signal and custom digital cores. Mac Add to Reading List Source URL: www.altos-da.com Language: English - Date: 2009-07-14 19:09:56 Altos Design Automation Logic design Mentor Graphics SPICE Logic simulation Electronic design automation Electronic engineering Digital electronics

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